; values in CAPS, self defined pointers and labels not,

	radix dec
	processor pic16f628a
	list n=0,st=off,mm=on

#include "p16f628a.inc" 

; initialize some preprocessor symbols
CONFIG_WORD = 0x3fff
OPTION_REG_CONFIG = 0

; set config word
CONFIG_WORD &= _CP_OFF & _DATA_CP_OFF	; turn all code protection off
CONFIG_WORD &= _LVP_OFF 		; disable Low Voltage Programming
CONFIG_WORD &= _BODEN_OFF		; disable Brown-out Detect Reset
CONFIG_WORD &= _MCLRE_OFF		; disable reset pin
CONFIG_WORD &= _PWRTE_ON		; enable power on timer
CONFIG_WORD &= _WDT_OFF			; disable Watchdog Timer
;CONFIG_WORD &= _INTRC_OSC_NOCLKOUT	; enable internal oscillator
CONFIG_WORD &= _HS_OSC			; enable external 20MHz crystal

	__config CONFIG_WORD

; USART buffers in bank 0
buf0		equ	0x20
buf1		equ	0x30
buf_size	equ	0x40 ; used by receiver
buf_len		equ	0x41 ; used during processing
address		equ	0x42 ; this chip's address
FSR_tmp		equ	0x43
usart_state	equ	0x44
usart_tmp0	equ	0x45
usart_tmp1	equ	0x46
profile_index	equ	0x47

dim0_ctr	equ	0x60
dim1_ctr	equ	0x61
dim2_ctr	equ	0x62
dim3_ctr	equ	0x63
;dim0_pres_ctr	equ	0x68
;dim1_pres_ctr	equ	0x69
;dim2_pres_ctr	equ	0x6A
;dim3_pres_ctr	equ	0x6B

; file registers in bank 0, 1, 2, 3
dim0_val	equ	0x70
dim1_val	equ	0x71
dim2_val	equ	0x72
dim3_val	equ	0x73
dim0_inc	equ	0x74
dim1_inc	equ	0x75
dim2_inc	equ	0x76
dim3_inc	equ	0x77
;dim0_pres_val	equ	0x78
;dim1_pres_val	equ	0x79
;dim2_pres_val	equ	0x7A
;dim3_pres_val	equ	0x7B
dim0_mode	equ	0x7C
dim1_mode	equ	0x7D
dim2_mode	equ	0x7E
dim3_mode	equ	0x7F
; some useful definitions
RA0		equ	0		; RA0 is bit zero in PORTA
RA1		equ	1		; etc
RA2		equ	2
RA3		equ	3
RB4		equ	4
RB5		equ	5

; pin assignments
; RA0	dim0
; RA1	dim1
; RA2	dim2
; RA3	dim3
; RA4	NOT CONNECTED
; RA5	ICSP programming voltage
; RA6	oscillator crystal
; RA7	oscillator crystal
; RB0	zero crossing interrupt on falling edge
; RB1	asynchronous serial receive
; RB2	asynchronous serial transmit (unused for now)
; RB3	NOT CONNECTED
; RB4	relais0
; RB5	relais1
; RB6	ICSP PCG
; RB7	ICPS PCD


	org 0x0000

reset_vector ; the chip starts executing our code here

	movlw 7<<CM0				; disable Comparators
	movwf CMCON

	clrf PORTA
	goto continue_init

	org 0x0004

interrupt_vector ; handler			; 4 (latency)

interrupt_tmr0
	btfss INTCON, T0IF 			; 2 (assume condition is met)
	goto interrupt_zero_crossing_entry

interrupt_tmr0_fake
	; tell TMR0 when we want the next interrupt
	movf profile_index, w			; 1
	call jumptable				; 6 = 2 + 2 + 2
	movwf TMR0				; 1

	; trigger some triacs...
	movlw b'00001111'			; 1
	incfsz dim0_ctr				; 2
	andlw b'00001110'
	incfsz dim1_ctr				; 2
	andlw b'00001101'
	incfsz dim2_ctr				; 2
	andlw b'00001011'
	incfsz dim3_ctr				; 2
	andlw b'00000111'
	iorwf PORTA, f				; 1

	decfsz profile_index, f			; 1 (assume condition is not true)
	goto interrupt_tmr0_exit		; 2

	; 100Hz interval finished, cleanup
	decf profile_index, f

	; ignore TMR0 interrupts
	bcf INTCON, T0IE ; stop running

	; and postpone next interrupt flag event for a long, long time
	clrf TMR0
	bcf INTCON, T0IF

	btfss usart_state, 7
	goto finished_processing_command

	movf FSR, w
	movwf FSR_tmp
	movlw 0x20
	movwf FSR
	btfss usart_state, 6
	bsf FSR, 4 ; reverse logic

	; store command
	movf INDF, w
	movwf usart_tmp0

	btfsc usart_tmp0, 7
	goto cmnd_bit7_is_1

	incf FSR
	movf INDF, w
	rrf usart_tmp0, f
	btfsc STATUS, C
	movwf dim0_val

	incf FSR
	movf INDF, w
	rrf usart_tmp0, f
	btfsc STATUS, C
	movwf dim1_val

	incf FSR
	movf INDF, w
	rrf usart_tmp0, f
	btfsc STATUS, C
	movwf dim2_val

	incf FSR
	movf INDF, w
	rrf usart_tmp0, f
	btfsc STATUS, C
	movwf dim3_val

	goto cmnd_cleanup

cmnd_bit7_is_1
	

cmnd_cleanup
	movf FSR_tmp, w
	movwf FSR

	bcf usart_state, 7

finished_processing_command
	; reinit dimmer counters

	movf FSR, w
	movwf FSR_tmp
	movlw 0x60
	movwf FSR

walk_dimmers
	bsf FSR, 4
	bsf FSR, 2
;	bsf FSR, 3
;	rrf INDF, w
;	bcf FSR, 3
	movf INDF, w
	bcf FSR, 2
	addwf INDF, f
	movf INDF, w
	bcf FSR, 4
	movwf INDF

	incf FSR
	btfss FSR, 2
	goto walk_dimmers

	
	movf FSR_tmp, w
	movwf FSR

	; switch off triac triggers
	movlw b'11110000' 
	andwf PORTA, f

interrupt_tmr0_exit

	bcf INTCON, T0IF			; 1

interrupt_tmr0_usart_receive ; only available after TMR0 interrupt
	btfss PIR1, RCIF			; 2
	goto interrupt_tmr0_tmr2 		; 1 (one cycle for free)

	btfsc RCSTA, OERR			; 2
	goto usart_receive_clear_ignore_set_state0 ; 1 (one cycle for free)

	btfsc RCSTA, FERR			; 2
	goto usart_receive_ignore_set_state0    ; 1 (one cycle for free)

	clrf usart_tmp0				; 1
	btfsc RCSTA, RX9D			; 2
	incf usart_tmp0				; 0 (free)
	movf RCREG, w				; 1
	movwf INDF				; 1
	xorwf usart_tmp0, f			; 1
	swapf usart_tmp0, w			; 1
	xorwf usart_tmp0, f			; 1
	rrf usart_tmp0, w			; 1
	xorwf usart_tmp0, f			; 1
	btfsc usart_tmp0, 2			; 2
	incf usart_tmp0, f			; 0 (free)

	btfsc usart_tmp0, 0			; 2
	goto usart_receive_set_state0		; 1 (one cycle for free)

	clrf TMR2
	bcf PIE1, TMR2IE
	incf FSR
	decfsz buf_size
	retfie

	; check if other buffer has been processed
	; - if so: mark this as 'to be processed' and switch to other
	; - of not so: reset FSR, discard this buffer

	movlw 0xC0
	btfss usart_state, 7    ; if set, buffer is not yet processed, so don't switch
	xorwf usart_state, f	; switch, because other buffer is free, also: set bit 7 to 1

	; move pointer to start of buffer
	movlw 0x20
	movwf FSR
	btfsc usart_state, 6
	bsf FSR, 4

	; we expect 4 bytes
	movlw 5
	movwf buf_size
	retfie

usart_receive_clear_ignore_set_state0
	bcf RCSTA, CREN				; 1
	bsf RCSTA, CREN ; clear oerr		; 1

usart_receive_ignore_set_state0
	movf RCREG, w				; 1

usart_receive_set_state0

	; set state0
	movwf 0xF8				; 1
	andwf usart_state, f			; 1
	retfie					; 2


interrupt_tmr0_tmr2 ; only available after TMR0 interrupt
	btfss PIR1, TMR2IF			; 2
	retfie

	movlw 5
	movwf buf_size
	movlw 0xF8
	andwf usart_state, f

	; move pointer to start of buffer
	movlw 0x20
	movwf FSR
	btfsc usart_state, 6
	bsf FSR, 4

	bcf PIR1, TMR2IF
	retfie

interrupt_zero_crossing_entry
	; 100Hz zero crossing interrupt (RB0/INT, falling edge)
	btfss INTCON, INTF
	retfie

	movlw 0xFF
	movwf profile_index

	clrf TMR0
	bsf INTCON, T0IE
	bcf INTCON, T0IF

interrupt_zero_crossing_exit
	bcf INTCON, INTF	; clear interrupt flag

	; after a zero crossing, fake a TMR0 interrupt
	goto interrupt_tmr0_fake

continue_init
	clrf PORTB

	bsf STATUS, RP0		; switch to bank 1

	movlw b'11110000'	; RA3:RA0 are outputs
	movwf TRISA

	movlw b'11001111'	; RB5:RB4 are outputs
	movwf TRISB

	; configure OPTION register
OPTION_REG_CONFIG |= 1<<NOT_RBPU	; disable Weak Pull Up
OPTION_REG_CONFIG &= ~1<<INTEDG		; int on falling edge
OPTION_REG_CONFIG &= ~1<<PSA		; assign prescaler to TMR0
OPTION_REG_CONFIG |= 4<<PS0		; set prescaler 1:32

	movlw OPTION_REG_CONFIG
	movwf OPTION_REG

	; async serial receiver
	movlw 139
	movwf SPBRG ; rate 20MHz/64/140 = 2232.142857 bps
	; dont enable interrupt generation, we poll RCIF at the end of
	; all TMR0 interrupts

	movlw 1<<TX9|1<<TXEN|0<<SYNC
	movwf TXSTA

	bcf STATUS, RP0		; switch to bank 0

	movlw 1<<SPEN|1<<RX9|1<<CREN|0<<ADEN
	movwf RCSTA

	; initialize special locations
	movlw 0x60
	movwf FSR
clear
	clrf INDF
	incf FSR
	btfss FSR, 7
	goto clear

	;movlw 0x05
	;movwf dim1_inc
	;movwf dim2_inc
	;movlw 0x7F
	;movwf dim1_val


	; initialize reception state machine
	clrf usart_state
	movlw 0x20
	movwf FSR
	movlw 5
	movwf buf_size
	
	movlw 0xFF
	movwf profile_index	; initialize profile read location

	; we use timer2 to detect reception timeouts on serial
	movlw 15<<TOUTPS0|1<<TMR2ON|2<<T2CKPS0
	movwf T2CON

	; use table at 0x300 for dimming
	movlw 3
	;; use table at 0x200 for dimming
	;movlw 2
	movwf PCLATH

	clrf TMR0
	movlw 1<<GIE|1<<INTE
	movwf INTCON

	; the rest is completely interrupt driven
burn_cycles
	goto burn_cycles

jumptable
	movwf PCL

	org 0x100
	
	org 0x200

#include "timing_power.inc" 			; 2

	org 0x300

#include "timing_db.inc" 			; 2

	end