; values in CAPS, self defined pointers and labels not,
; optimize for size rather than speed

	radix dec
	processor pic12f675
	list n=0,st=off

#include "p12f675.inc"

CONFIG_WORD = 0x3fff
OPTION_REG_CONFIG = 0

; set config word
CONFIG_WORD &= _CPD_OFF & _CP_OFF	; turn all code protection off
CONFIG_WORD &= _BODEN_ON		; enable Brown-out Detect Reset
CONFIG_WORD &= _MCLRE_OFF		; enable GP3 digital input
CONFIG_WORD &= _PWRTE_ON		; enable power on timer
CONFIG_WORD &= _WDT_OFF			; disable Watchdog Timer
CONFIG_WORD &= _INTRC_OSC_NOCLKOUT	; use internal OSC, freeup GP4 and GP5

	__config CONFIG_WORD

; file registers in bank 0,1
dim0_ctr	equ	0x20		; gets incremented until overflow
dim1_ctr	equ	0x21		; dimX is turned on at overflow
dim0_val	equ	0x22		; _ctr is reset to _val at INT
dim1_val	equ	0x23		; (INT is zero crossing)
io_buf_hi	equ	0x24		; io buffer (HIGH)
io_buf_lo	equ	0x25		; io buffer (LOW)
io_buf_bits	equ	0x26		; amount of bits in buffer

	org 0x0000

reset_vector	; the chip starts executing our code here
	
	; interrrupts are disabled by default, we are in bank 0

	movlw 1<<CM2|1<<CM1|1<<CM0	; disable Comparators
	movwf CMCON

	clrf GPIO			; init all outputs to 0

	goto continue_init		; skip interrupt handler

interrupt_vector ; handler (0x0004)

	; 100Hz zero crossing interrupt (GP2/INT, rising edge)
	btfss INTCON, INTF
	goto interrupt_TMR0

	; we got a zero crossing, turn off GP5:GP4, reset counters
	; trigger timer interrupt by setting timer to 0xff
	clrf GPIO

	movf dim0_val, w
	movwf dim0_ctr
	movf dim1_val, w
	movwf dim1_ctr

	movlw 0xFF 	; assume real zero crossing is right after this,
			; this constant may need to be lowered if not
	movwf TMR0

	; read potmeter 
	bsf ADCON0, GO_DONE

	bcf INTCON, INTF	; clear interrupt flag

interrupt_TMR0

	; is triggered approximately 25600 times per second, it decides
	; to put GP5:GP4 high at the right time
	btfss INTCON, T0IF
	goto interrupt_ADC

interrupt_TMR0_dim0
	incfsz dim1_ctr
	goto interrupt_TMR0_dim1

	bsf GPIO, GP4

interrupt_TMR0_dim1
	incfsz dim0_ctr
	goto interrupt_TMR0_adjust

	bsf GPIO, GP5


interrupt_TMR0_adjust

	; each period of 100Hz*256 has 39.0625 clockcycles, so we add 217
	; to TMR0 to get the next interrupt on time

	movf TMR0, w
	;addlw 218 ; the +1 accounts for 2 cycles no change and the additiontime
	addlw 218 ; the +1 accounts for 2 cycles no change and the additiontime
	movwf TMR0

	bcf INTCON, T0IF	; clear interrupt flag

interrupt_ADC
	
	; read from the ADC, and decide what to do
	btfss PIR1, ADIF
	goto interrupt_IO

	movf ADRESH, w
	movwf dim0_val
	movwf dim1_val

	bcf PIR1, ADIF		; clear interrupt flag

interrupt_IO

	; data IO, read a bit, and see if we have enough
	;btfss INTCON, GPIF
	retfie	; bogus interrupt??!?!?!
	
	btfsc GPIO, GP1
	goto interrupt_IO_end

	incf dim1_val

	
	bsf STATUS, C
	btfss GPIO, GP1
	bcf STATUS, C
	
	rrf io_buf_hi
	rrf io_buf_lo

	decfsz io_buf_bits
	goto interrupt_IO_end

	movf io_buf_hi, w
	movwf dim1_val
	
	bsf io_buf_bits, 3

interrupt_IO_end
	movf GPIO, f
	bcf INTCON, GPIF
	retfie

continue_init

	bsf ADCON0, ADON		; switch A/D converter on
					; all other bits are correct

	bsf PIE1, ADIE			; enable AD converter interrupt

	bsf STATUS, RP0			; switch to bank 1

	call 0x03ff			; retrieve factory OSCCAL value
	movwf OSCCAL			; write it to the right place

	movlw 1<<ADCS2|1<<ADCS0|1<<ANS0	; user Fosc/16, and AN0 as analog input
	movwf ANSEL

	; pin 7: AN0 analog input (dimmer dial)
	; pin 6: GP1 digital input, PC clock, interrupt on change
	; pin 5: INT zero crossing detector, rising edge interrupt (digital in)
	; pin 4: GP3 digital input, PC data
	; pin 3: GP4 digital output, controls dim0
	; pin 2: GP5 digital output, controls dim1

	movlw b'11001111'
	movwf TRISIO

	bsf IOC, GP1	; enable interrupt on change for GP1 (disabled on RESET)

	; we only care about these bits in OPTION_REG
OPTION_REG_CONFIG |= 1<<NOT_GPPU	; disable Weak Pull Up
OPTION_REG_CONFIG |= 1<<INTEDG		; interrupt in rising edge of INT
OPTION_REG_CONFIG &= ~1<<T0CS		; Timer0 clock source = internal
OPTION_REG_CONFIG |= 1<<PSA		; assign prescaler to WDT

	movlw OPTION_REG_CONFIG
	movwf OPTION_REG

	bcf STATUS, RP0			; switch to bank 0

; after init
	movlw 0xFF
	movwf dim0_val
	movlw 0xFF
	movwf dim1_val
	movlw 0x08
	movwf io_buf_bits
	clrf dim0_ctr
	clrf dim1_ctr
	clrf TMR0

	; enable INT/GP2, T0, External and 'GPIO change' interrupts
	movlw 1<<GIE|1<<T0IE|1<<INTE|1<<PEIE ;|GPIE<<1
	movwf INTCON

	; the rest is completely interrupt driven
burn_cycles
	goto burn_cycles

	end