; values in CAPS, self defined pointers and labels not,
; optimize for size rather than speed

	radix dec
	processor pic16f627
	list n=0,st=off

#include "p16f627.inc"

CONFIG_WORD = 0x3fff
OPTION_REG_CONFIG = 0

; set config word
CONFIG_WORD &= _CP_OFF & _DATA_CP_OFF	; turn all code protection off
CONFIG_WORD &= _LVP_OFF			; disable Low Voltage Programming
CONFIG_WORD &= _BODEN_ON		; enable Brown-out Detect Reset
CONFIG_WORD &= _MCLRE_OFF		; enable RA5 digital input
CONFIG_WORD &= _PWRTE_ON		; enable power on timer
CONFIG_WORD &= _WDT_OFF			; disable Watchdog Timer
CONFIG_WORD &= _INTRC_OSC_NOCLKOUT	; use internal OSC, freeup RB7:RB6

	__config CONFIG_WORD

; file registers in bank 0,1,2,3
dim_ctr		equ	0x70		; gets incremented until overflow
dim_val		equ	0x71		; _ctr is reset to _val at INT
dim_delta	equ	0x72		; dim_delta
dim_slow	equ     0x73

	org 0x0000

reset_vector	; the chip starts executing our code here
	
	; interrrupts are disabled by default, we are in bank 0

	movlw 1<<CM2|1<<CM1|1<<CM0	; disable Comparators
	movwf CMCON

	clrf PORTA			; init PORTA outputs to 0

	goto continue_init		; skip interrupt handler

interrupt_vector ; handler (0x0004)

	; 100Hz zero crossing interrupt (RB0/INT, rising edge)
	btfss INTCON, INTF
	goto interrupt_TMR0

	; we got a zero crossing, 

	; turn off RA1:RA0, reset counters
	; trigger timer interrupt by setting timer to 0xff
	clrf PORTA

	movf dim_val, w

	decfsz dim_slow
	goto tru2

	bsf dim_slow, 2

	addwf dim_delta, w
	btfss dim_delta, 7
	goto dim_higher
	
	; lower
	btfsc STATUS, C
	goto tru

	clrf dim_delta
	clrw
	goto tru

dim_higher
	btfss STATUS, C
	goto tru

	clrf dim_delta
	movlw 0xFF

tru
	movwf dim_val
tru2
	movwf dim_ctr

	movlw 0xFF 	; assume real zero crossing is right after this,
			; this constant may need to be lowered if not
	movwf TMR0

	bcf INTCON, INTF	; clear interrupt flag

interrupt_TMR0
	; is triggered approximately 25600 times per second, it decides
	; to put RA1:RA0 high at the right time
	btfss INTCON, T0IF
	goto interrupt_IO

interrupt_TMR0_dim
	incfsz dim_ctr
	goto interrupt_TMR0_adjust

	bsf PORTA, 0
	bsf PORTA, 1

interrupt_TMR0_adjust

	; each period of 100Hz*256 has 39.0625 clockcycles, so we add 217
	; to TMR0 to get the next interrupt on time

	movf TMR0, w
	addlw 218 ; the +1 accounts for 2 cycles no change and the additiontime
	movwf TMR0

	; handle timeout
	;incfsz io_timeout
	;goto io_timeout_ok

	;movlw 0x8;
	;movwf io_buf_bits;
;io_timeout_ok

	bcf INTCON, T0IF	; clear interrupt flag


interrupt_IO
	btfss INTCON, RBIF
	retfie	; bogus interrupt??!?!?!

	; data IO, read a bit, and see if we have enough
	
	btfss PORTB, 3
	goto io_delta_dec
	
	incf dim_delta
	goto interrupt_IO_end

io_delta_dec
	decf dim_delta
	goto interrupt_IO_end

interrupt_IO_end
	bcf INTCON, RBIF
	retfie

continue_init

	bsf STATUS, RP0			; switch to bank 1

	; pin 12: RB6 digital input, PC clock, interrupt on change
	; pin  6: INT zero crossing detector, rising edge interrupt (digital in)
	; pin  9: RB3 digital input, PC data
	; pin 17: RA0 digital output, controls dim0
	; pin 18: RA1 digital output, controls dim1

	movlw b'11111100'
	movwf TRISA

	; we only care about these bits in OPTION_REG
OPTION_REG_CONFIG &= ~1<<NOT_RBPU	; enable Weak Pull Up
OPTION_REG_CONFIG |= 1<<INTEDG		; interrupt in rising edge of INT
OPTION_REG_CONFIG &= ~1<<T0CS		; Timer0 clock source = internal
OPTION_REG_CONFIG |= 1<<PSA		; assign prescaler to WDT

	movlw OPTION_REG_CONFIG
	movwf OPTION_REG

	bcf STATUS, RP0			; switch to bank 0

; after chip init
	movlw 0x80
	movwf dim_val
	clrf dim_delta

	clrf dim_ctr
	clrf TMR0

	movlw 0x04
	movwf dim_slow

	;movf PORTB, f ; read PORTB before enabling RBI
	; enable INT/RB0, T0 and RB7:RB4 change interrupt
	movlw 1<<GIE|1<<INTE|1<<T0IE|1<<RBIE
	movwf INTCON

	; the rest is completely interrupt driven
burn_cycles
	goto burn_cycles

	end